1. Field of the Invention
The present invention relates generally to a driver for interfacing integrated circuits (ICs) to transmission lines, and more specifically to such a driver which is able to effectively reduce switching transients induced in a transmitting signal due to parasitic components.
2. Description of the Related
A digital system such as a computer and the like includes a plurality of IC devices which are interconnected for binary communications by transmission lines. Each IC device is provided with a driver and/or receiver for interfacing ICs of the device to the transmission lines.
Before turning to the present invention it is deemed preferable to discuss a conventional driver with reference to FIGS. 1 and 2. In the drawings attached to the specification, like elements or portions are denoted by like reference numerals.
FIG. 1 is a block diagram schematically showing IC devices 10 and 12 which are coupled via the package terminals thereof to a bus 14. Although not shown in FIG. 1, the bus 14 is comprised of a plurality of transmission lines as is well known in the art. For the sake of simplifying the disclosure, each of the IC devices 10 and 12 has only four terminals 16a-16d which are relevant to the present invention.
As shown in FIG. 1, the terminals 16a-16d of the IC device 10 or 12 are respectively assigned to a data output terminal (OUT), power source terminal (VDD), data input terminal (IN), and ground terminal (GND).
The bus 14 usually is microstrip lines formed on a suitable substrate such as a PCB (printed circuit board)(not shown). Similarly, the lines extending from the package terminals 16a-16d are typically formed on a substrate on which the IC devices 10 and 12 are mounted.
As is known in the art, with a bus of substantial length, it is common to "terminate" data transmission lines at their opposite ends with a resistive pullup or pulldown. That is, each transmission line of the bus 14, which has relatively low characteristic impedance on the order of about 50.OMEGA.-70.OMEGA., has opposite ends coupled to resistors 20 and 22 for terminating in the line's characteristic impedance. The bus terminating resistors 20 and 22 are respectively connected, via terminals 24 and 26, to source voltage (+V) on the order of about 1.2 V-2.0 V (for example).
FIG. 2 is a block diagram schematically showing an arrangement inside the IC device 10 (or 12), which includes a driver 30 to which the present invention is applied. The driver 30 is disclosed in U.S. Pat. No. 5,023,488 to William F. Gunning.
The IC device 10 includes, in addition to the aforesaid driver 30, a plurality of integrated circuits which are collectively depicted by block 34. The driver 30 receives binary information from the block 34 via an input terminal 36 and interfaces the block 34 to the bus 14 (FIG. 1). The driver 30 and the IC block 34 are formed on the same IC chip. Rectangular notations 38a-38d indicate "contact pads" formed on the IC chip, which pads are electrically coupled to the corresponding package terminals 16a-16d via respective bonding wires 40a-40d of aluminum or gold. More specifically, the IC chip pad 38a is the output terminal of the driver 30. Electrical elements enclosed by broken lines 42a and 42b indicate parasitic components which from noticeable ringing circuits especially when an N-channel CMOS transistor 43 of the driver 30 is switched from a conductive state to a non-conductive state. These ringing circuits are liable to cause the voltage on the transmission line 14 (FIG. 1) to oscillate around the terminating voltage +V (FIG. 1) for a prolonged period time.
In the drawings attached to the instant specification, capital letters "D" and "S" respectively indicate "drain" and "source" terminals of CMOS transistors.
In order to reduce the switching transients resulting from the parasitic components 42a-42b, the driver 30 is provided with a feedback path and a delay circuit. The feedback path includes two N-channel CMOS transistors 54 and 56, while the delay circuit includes two inverters 58 and 60.
In addition, the driver 30 includes another inverter which includes a P-channel CMOS transistor 62 and an N-channel CMOS transistor 64. Reference numerals 66 and 68 depict respectively a power line and a ground line both formed on the IC chip including the driver 30 and the block 34.
The operation of the driver 30 of FIG. 2 is described.
A low logic level signal at the input terminal 36 holds the P-channel CMOS transistor 62 in a conductive state and the N-channel CMOS transistors 64 and 56 in a non-conductive state. Thus, the N-channel CMOS transistor 54 is in a conductive state. This means that the feedback path (54, 56) is not established while the low logic level appears at the input terminal 36.
However, shortly after the logic level of the signal at the input terminal 36 is raised to a logic high level, the transistors 62 and 64 are respectively rendered non-conductive and conductive. Thus, the transistor 64 tends to pull the gate of the N-channel transistor 43 down toward ground. At the same time, the transistor 56 is switched into conduction so that it establishes a feedback path between the drain and the gate of the transistor 43. Thus, the feedback path prevents the drain voltage of the transistor 43 (viz., the voltage at the output terminal 38a) from increasing to a level significantly above its gate voltage. This limits the rate at which the current flowing through the parasitic components 42a and 42b (especially 42a). It follows that the undesirable oscillation (viz., switching transients) of the transmitting signal appearing at the bus 14 is reduced. Finally, about one or few nanoseconds after the transistor 56 is rendered conductive, the output of the inverter 60 drops to the low logic level. Therefore, the transistor 54 is switched into a non-conductive state so that the feedback path is re-opened thereby permitting the transistor 43 to switch completely out of conduction.
The amplitude of the signal being transmitted over the bus 14 is determined by: (a) parallel resistance of the bus line's characteristic impedance and the resistance of the terminating resistors 20 and 22, (b) the terminating voltage +V, and (c) a divided voltage (at the output terminal 38a) defined by the resistance of the open drain CMOS transistor 43. When the bus terminating voltage +V is 1.2 V, the logic voltage swing becomes about 0.8 V. Since the high logic level is 1.2 V in this case, the low logic level becomes 0.4 V (=1.2 V-0.8 V).
It is assumed that the IC device 10 outputs a logic signal which is transmitted to the IC device 12 over the bus 14. The IC device 12 includes a receiver (not shown) which discriminates whether the logic level received is high ("1") or low ("0") using an input threshold. The input threshold is usually set to an intermediate point of the above mentioned logic voltage swing. That is, the intermediate point is set to 0.8 V (=(1.2 V-0.8 V)+0.4 V) in the above case. At a time point after the receiver acquires the logic signal, the receiver determines whether the logic signal received is high or low. This is done by defining, at the logic level determining time point, if the logic signal level is above or below the input threshold. This means that the aforesaid oscillation (viz., ranging) of the output signal of the driver 30 should be damped as early as possible.
The inventor conducted computer simulation to study how the output of the driver 30 oscillates when a high logic level is applied to the input terminal 36. The result of the simulation is shown in FIG. 3 wherein a legend "INPUT" indicates the signal applied to the input terminal 36 while "OUTPUT" indicates the output of the driver 30 (viz., the logic signal appearing at the bus 14). As shown, the output significantly swings upward and downward shortly after the input is applied to the terminal 36, resulting in relatively large "overshoot" and "backswing". More specifically, the output of the driver 30 crosses several times the input threshold (0.8 V) and thus, the receiver (not shown) of the IC device (12 for example) is unable to ascertain the logic level until the output of the driver 30 stops the crossing of the input threshold. In other words, with the driver 30 of FIG. 2, a propagation delay Tpd is noticeably large.
We have thus far discussed the parasitic components related to the IC package. However, as shown in FIG. 4, when the low logic level jumps to the high level, a plurality of inductive and resistive parasitic components L1, L2, . . . , Ln and R1, R2, . . . , Rn are developed in series with the bus line 14, while capacitive parasitic components C1, C2, . . . , Cn are induced between the bus line 14 and the ground line formed on the PCB which carries the IC devices 10 and 12. These bus-side parasitic elements tends to enhance the above mentioned undesirable oscillation.